論文誌
[1] T. Nakayama and M. Hashimoto, "Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume 102-A, number 7, pages 914--917, July 2019.
[2] T. Sato, J. Ichimiya, N. Ono, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3382-3389, December 2005.
国際会議
[1] T. Nakayama and M. Hashimoto, "Hold Violation Analysis for Functional Test of Ultra-Low Temperature Circuits at Room Temperature," Proceedings of International Symposium on VLSI Design, Automation and Test (VLSI-DAT), April 2018.
[2] T. Sato, N. Ono, J. Ichimiya, K. Hachiya, and M. Hashimoto, "On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1074-1077, January 2005.