論文誌
[1] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3585-3593, December 2006.
[2] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3560-3568, December 2006.
[3] A. Kurokawa, M. Hashimoto, A. Kasebe, Z.-C. Huang, Y. Yang, Y. Inoue, R. Inagaki, and H. Masuda, "Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 12, pages 3453-3462, December 2005.
[4] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Representative Frequency for Interconnect R(f)L(f)C Extraction," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E86-A, number 12, pages 2942-2951, December 2003.
国際会議
[1] M. Hashimoto, Y. Nakazawa, R. Doi, and J. Yu, "Interconnect Delay Analysis for RRAM Crossbar Based FPGA (Invited)," Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2018.
[2] J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, and M. Hashimoto, "A Highly-Dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect Using Via-Switch," Proceedings of International Conference on Field Programmable Logic and Applications (FPL), August 2016.
[3] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pages 227-230, May 2006.
[4] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Interconnect RL Extraction at a Single Representative Frequency," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 515-520, January 2006.
[5] Y. Uchida, S. Tani, M. Hashimoto, S. Tsukiyama, and I. Shirakawa, "Interconnect Capacitance Extraction for System LCD Circuits," In Proceedings of Great Lakes Symposium on VLSI (GLSVLSI), pages 160-163, April 2005.
[6] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Representative Frequency for Interconnect R(f)L(f)C Extraction," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 691-696, January 2004.
[7] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Frequency Determination for Interconnect RLC Extraction," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 288-293, April 2003.