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Table of works

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	著者名 (author)	表題 (title)	論文誌/会議名	巻号	ページ範囲 (pages)	出版年月	File
論文誌	H. Itsuji, T. Uezono, T. Toba, K. Ito, M. Hashimoto	A Hardware-Aware Failure-Detection Method for GPU Control-Logic	IEEE Access			採録済
論文誌	R. Sada, T. Tanaka, H. Asaue, T. Shiotani, M. Hashimoto, R. Shirai	Localization of Embedded Sensors in Reinforced Concrete Via Time-Series Magnetic Field Sensing and Maximum Likelihood Estimation	IEEE Sensors Letters			採録済
論文誌	K. Takeuchi, K. Sakamoto, Y. Tsuchiya, T. Kato, R. Nakamura, A. Takeyama, T. Makino, T. Ohshima, M. Hashimoto, H. Shindo	Cross-Section Prediction Method for Proton Direct Ionization Induced Single Event Upset	IEEE Transactions on Nuclear Science	72(8)	2735 - 2742	2025年8月	pdf
論文誌	R. Fukugasako, H. Asaue, T. Shiotani, M. Hashimoto, R. Shirai	A Current Chopper-Assisted Magnetic Field-Based Backscatter Communication Method with WPT Overcoming Ultra-Low Coupling Coefficients	IEEE Sensors Journal	25(10)	18249-18256	2025年5月	pdf
論文誌	S. Abe, M. Hashimoto, W. Liao, T. Kato, H. Asai, K. Shimbo, H. Matsuyama, T. Sato, K. Kobayashi, Y. Watanabe	A Terrestrial SER Estimation Methodology Based on Simulation Coupled with One-Time Neutron Irradiation Testing	IEEE Transactions on Nuclear Science	70(8)	1652 -- 1657	2023年8月	pdf
論文誌	Y. Zhang, H. Itsuji, T. Uezono, T. Toba, M. Hashimoto	Vulnerability Estimation of DNN Model Parameters with Few Fault Injections	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E106-A(3)	523-531	2023年3月	pdf
論文誌	M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, T. Sugibayashi	Via-Switch FPGA with Transistor-Free Programmability Enabling Energy-Efficient Near-Memory Parallel Computation	Japanese Journal of Applied Physics	61(SM0804)		2022年10月	pdf
論文誌	X. Bai, N. Banno, M. Miyamura, R. Nebashi, K. Okamoto, H. Numata, N. Iguchi, M. Hashimoto, T. Sugibayashi, T. Sakamoto, M. Tada	Via-Switch FPGA: 65nm CMOS Implementation and Evaluation	IEEE Journal of Solid-State Circuits	57(7)	2250-2262	2022年7月	pdf
論文誌	T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, M. Hashimoto	Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E105-A(3)	497--508	2022年3月	pdf
論文誌	Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, , M. Hashimoto	Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	105-A(3)	509--517	2022年3月	pdf
論文誌	T. Tanaka, W. Liao, M. Hashimoto, Y. Mitsuyama	Impact of Neutron-Induced SEU in FPGA CRAM on Image-Based Lane Tracking for Autonomous Driving: from Bit Upset to SEFI and Erroneous Behavior	IEEE Transactions on Nuclear Science	69(1)	35--42	2022年1月	pdf
論文誌	K. Ito, Y. Zhang, H. Itsuji, T. Uezono, T. Toba, M. Hashimoto	Analyzing DUE Errors on GPUs with Neutron Irradiation Test and Fault Injection to Control Flow	IEEE Transactions on Nuclear Science	68(8)	1668--1674	2021年8月	pdf
論文誌	T. Kato, M. Tampo, S. Takeshita, H. Tanaka, H. Matsuyama, M. Hashimoto, Y. Miyake	Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization with Neutrons and Alpha Particles	IEEE Transactions on Nuclear Science	68(7)	1436-1444	2021年7月	pdf
論文誌	R. Doi, X. Bai, T. Sakamoto, M. Hashimoto	A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	103-A(12)	1447--1455	2020年12月	pdf
論文誌	T. Cheng, Y. Masuda, J. Chen, J. Yu, M. Hashimoto	Logarithm-Approximate Floating-Point Multiplier Is Applicable to Power-Efficient Neural Network Training	Integration, the VLSI Journal	74	19--31	2020年9月	pdf
論文誌	T. Mahara, S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, T. Y. Saito, M. Niikura, K. Ninomiya, D. Tomono, A. Sato	Irradiation Test of 65 nm Bulk SRAMs with DC Muon Beam at RCNP MuSIC Facility	IEEE Transactions on Nuclear Science	67(7)	1555 -- 1559	2020年7月	pdf
論文誌	T. Kato, M. Hashimoto, H. Matsuyama	Angular Sensitivity of Neutron-Induced Single-Event Upsets in 12-nm FinFET SRAMs with Comparison to 20-nm Planar SRAMs	IEEE Transactions on Nuclear Science	67(7)	1485 -- 1493	2020年7月	pdf
論文誌	J. Chen, H. Kando, T. Kanamoto, C. Zhuo, M. Hashimoto	A Multi-Core Chip Load Model for PDN Analysis Considering Voltage-Current-Timing Interdependency and Operation Mode Transitions	IEEE Transactions on Components, Packaging and Manufacturing Technology	9(9)	1669--1679	2019年9月	pdf
論文誌	N. Banno, K. Okamoto, N. Iguchi, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi, T. Sakamoto, M. Tada	Low-Power Crossbar Switch with Two-Varistors Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA	IEEE Transactions on Electron Devices	66(8)	3331--3336	2019年8月	pdf
論文誌	T. Nakayama, M. Hashimoto	Stochastic Analysis on Hold Timing Violation in Ultra-Low Temperature Circuits for Functional Test at Room Temperature	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	102-A(7)	914--917	2019年7月	pdf
論文誌	S. Abe, W. Liao, S. Manabe, T. Sato, M. Hashimoto, Y. Watanabe	Impact of Irradiation Side on Neutron-Induced Single Event Upsets in 65-nm Bulk SRAMs	IEEE Transactions on Nuclear Science	66(7)	1374 -- 1380	2019年7月	pdf
論文誌	H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, T. Sakamoto	Sensor Signal Processing Using High-Level Synthesis with a Layered Architecture	IEEE Embedded Systems Letters	10(4)	119 -- 122	2018年12月	desc
論文誌	H. Ochi, K. Yamaguchi, T. Fujimoto, J. Hotate, T. Kishimoto, T. Higashi, T. Imagawa, R. Doi, M. Tada, T. Sugibayashi, W. Takahashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, J. Yu, M. Hashimoto	Via-Switch FPGA: Highly-Dense Mixed-Grained Reconfigurable Architecture with Overlay Via-Switch Crossbars	IEEE Transactions on VLSI Systems	26(12)	2723--2736	2018年12月	pdf
論文誌	Y. Masuda, T. Onoye, M. Hashimoto	Activation-Aware Slack Assignment for Time-To-Failure Extension and Power Saving	IEEE Transactions on VLSI Systems	26(11)	2217--2229	2018年11月	pdf
論文誌	K. Mitsunari, J. Yu, T. Onoye, M. Hashimoto	Hardware Architecture for High-Speed Object Detection Using Decision Tree Ensemble	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E101-A(9)	1298--1307	2018年9月	pdf
論文誌	S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, S. Abe, K. Hamada, M. Tampo, Y. Miyake	Negative and Positive Muon-Induced Single Event Upsets in 65-nm UTBB SOI SRAMs	IEEE Transactions on Nuclear Science	65(8)	1742--1749	2018年8月	pdf
論文誌	W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, Y. Miyake	Measurement and Mechanism Investigation of Negative and Positive Muon-Induced Upsets in 65-nm Bulk SRAMs	IEEE Transactions on Nuclear Science	65(8)	1734--1741	2018年8月	pdf
論文誌	R. Doi, M. Hashimoto, T. Onoye	An Analytic Evaluation on Soft Error Immunity Enhancement Due to Temporal Triplication	International Journal of Embedded Systems	10(1)	22-31	2018年1月
論文誌	Y. Masuda, T. Onoye, M. Hashimoto	Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E100-A(7)	1452--1463	2017年7月	pdf
論文誌	S. Iizuka, Y. Higuchi, M. Hashimoto, T. Onoye	Device-Parameter Estimation with Sensitivity-Configurable Ring Oscillator	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E98-A(12)	2607--2613	2015年12月
論文誌	T. Shinada, M. Hashimoto, T. Onoye	Proximity Distance Estimation Based on Electric Field Communication between 1mm³ Sensor Nodes	Analog Integrated Circuits and Signal Processing			2015年5月	220.pdf
論文誌	S. Hirokawa, R. Harada, M. Hashimoto, T. Onoye	Characterizing Alpha- and Neutron-Induced SEU and MCU on SOTB and Bulk 0.4-V SRAMs	IEEE Transactions on Nuclear Science	62(2)	420--427	2015年4月	219.pdf
論文誌	T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, M. Hashimoto	Exploring Well-Configurations for Minimizing Single Event Latchup	IEEE Transactions on Nuclear Science	61(6)	3282--3289	2014年12月	211.pdf
論文誌	H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, M. Hashimoto, T. Onoye, H. Onodera	Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E97-A(12)	2518--2529	2014年12月	210.pdf
論文誌	T. Amaki, M. Hashimoto, T. Onoye	A Process and Temperature Tolerant Oscillator-Based True Random Number Generator	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E97-A(12)	2393--2399	2014年12月	208.pdf
論文誌	H. Konoura, T. Imagawa, Y. Mitsuyama, M. Hashimoto, T. Onoye	Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E97-A(7)	1468--1482	2014年7月	201.pdf
論文誌	H. Konoura, T. Kameda, Y. Mitsuyama, M. Hashimoto, T. Onoye	NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E97-A(7)	1483--1491	2014年7月	202.pdf
論文誌	R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye	SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E97-A(7)	1461--1467	2014年7月	200.pdf
論文誌	H. Fuketa, R. Harada, M. Hashimoto, T. Onoye	Measurement and Analysis of Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 10T Subthreshold SRAM	IEEE Transactions on Device and Materials Reliability	14(1)	463 -- 470	2014年3月	185.pdf
論文誌	T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto	Mitigating Multi-Bit-Upset with Well-Slits in 28 nm Multi-Bit-Latch	IEEE Transactions on Nuclear Science	60(6)	4362--4367	2013年12月	197.pdf
論文誌	T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto	Soft-Error in SRAM at Ultra-Low Voltage and Impact of Secondary Proton in Terrestrial Environment	IEEE Transactions on Nuclear Science	60(6)	4232--4237	2013年12月	198.pdf
論文誌	D. Alnajjar, H. Konoura, Y. Ko, Y. Mitsuyama, M. Hashimoto, T. Onoye	Implementing Flexible Reliability in a Coarse Grained Reconfigurable Architecture	IEEE Transactions on VLSI Systems	21(12)	2165 -- 2178	2013年12月	177.pdf
論文誌	K. Shinkai, M. Hashimoto, T. Onoye	A Gate-Delay Model Focusing on Current Fluctuation Over Wide Range of Process-Voltage-Temperature Variations	Integration, the VLSI Journal	46(4)	345--358	2013年9月	179.pdf
論文誌	T.Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye	Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices	IEICE Trans. on Information and Systems	E96-D(8)	1624--1631	2013年8月	191.pdf
論文誌	T. Amaki, M. Hashimoto, Y. Mitsuyama, T. Onoye	A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator with Stochastic Behavior Modeling	IEEE Transactions on Information Forensics and Security	8(8)	1331--1342	2013年8月	190.pdf
論文誌	R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye	Impact of NBTI-Induced Pulse-Width Modulation on SET Pulse-Width Measurement	IEEE Transactions on Nuclear Science	60(4)	2630--2634	2013年8月	180.pdf
論文誌	D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye	PVT-induced Timing Error Detection Through Replica Circuits and Time Redundancy in Reconfigurable Devices	IEICE Electronics Express (ELEX)	10(5)		2013年4月	184.pdf
論文誌	Y. Ogasahara, M. Hashimoto, T. Kanamoto, T. Onoye	Supply Noise Suppression by Triple-Well Structure	IEEE Transactions on VLSI Systems	21(4)	781--785	2013年4月	169.pdf
論文誌	I. Homjakovs, T. Hirose, Y. Osaki, M. Hashimoto, T. Onoye	A 0.8-V 110-nA CMOS Current Reference Circuit Using Subthreshold Operation	IEICE Electronics Express (ELEX)	10(4)		2013年3月	182.pdf
論文誌	T. Amaki, M. Hashimoto, T. Onoye	Jitter Amplifier for Oscillator-Based True Random Number Generator	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E96-A(3)	684--696	2013年3月	181.pdf
論文誌	I. Homjakovs, M. Hashimoto, T. Hirose, T. Onoye	Signal-Dependent Analog-To-Digital Conversion Based on MINIMAX Sampling	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E96-A(2)	459--468	2013年2月	178.pdf
論文誌	R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, Y. Watanabe	Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM	IEEE Transactions on Nuclear Science	59(6)	2791--2795	2012年12月	175.pdf
論文誌	T. Enami, T. Sato, M. Hashimoto	Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E95-A(12)	2261--2271	2012年12月	171.pdf
論文誌	Y. Takai, M. Hashimoto, T. Onoye	Power Gating Implementation for Supply Noise Mitigation with Body-Tied Triple-Well Structure	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E95-A(12)	2220--2225	2012年12月	172.pdf
論文誌	S. Kimura, M. Hashimoto, T. Onoye	A Body Bias Clustering Method for Low Test-Cost Post-Silicon Tuning	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E95-A(12)	2292--2300	2012年12月	173.pdf
論文誌	H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye	Adaptive Performance Compensation with In-Situ Timing Error Predictive Sensors for Subthreshold Circuits	IEEE Transactions on VLSI Systems	20(2)	333--343	2012年2月	155.pdf
論文誌	H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye	Stress Probability Computation for Estimating NBTI-Induced Delay Degradation	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E94-A(12)	2545--2553	2011年12月	166.pdf
論文誌	K. Shinkai, M. Hashimoto, T. Onoye	Extracting Device-Parameter Variations with RO-Based Sensors	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E94-A(12)	2537--2544	2011年12月	165.pdf
論文誌	T. Okumura, M. Hashimoto	Setup Time, Hold Time and Clock-To-Q Delay Computation under Dynamic Supply Noise	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E94-A(10)	1948--1953	2011年10月	164.pdf
論文誌	H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye	Neutron-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM	IEEE Transactions on Nuclear Science	58(4)	2097--2102	2011年8月	159.pdf
論文誌	H. Fuketa, D. Kuroda, M. Hashimoto, T. Onoye	An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion	IEEE Transactions on Circuits and Systems II	58(5)	299--303	2011年5月	158.pdf
論文誌	R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye	Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-inverter-delay Resolution	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E93-A(12)	2417--2423	2010年12月	149.pdf
論文誌	T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, M. Hashimoto	Gate Delay Estimation in STA under Dynamic Power Supply Noise	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E93-A(12)	2447--2455	2010年12月	151.pdf
論文誌	T. Enami, K. Shinkai, S. Ninomiya, S. Abe, M. Hashimoto	Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E93-A(12)	2399--2408	2010年12月	148.pdf
論文誌	H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye	Transistor Variability Modeling and Its Validation with Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits	IEEE Transactions on VLSI Systems	18(7)	1118--1129	2010年7月	130.pdf
論文誌	T. Kanamoto, T. Okumura, K. Furukawa, H. Takafuji, A. Kurokawa, K. Hachiya, T. Sakata, M. Tanaka, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto	Impact of Self-Heating in Wire Interconnection on Timing	IEICE Trans. on Electronics	E93-C(3)	388--392	2010年3月	136.pdf
論文誌	K. Shinkai, M. Hashimoto, T. Onoye	Prediction of Self-Heating in Short Intra-Block Wires	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E93-A(3)	583--594	2010年3月	135.pdf
論文誌	Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, Y. Inoue	Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems	29(2)	250--260	2010年2月	134.pdf
論文誌	H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye	Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E92-A(12)	3094--3102	2009年12月	128.pdf
論文誌	T. Sakata, T. Okumura, A. Kurokawa, H. Nakashima, H. Masuda, T. Sato, M. Hashimoto, K. Hachiya, K. Furukawa, M. Tanaka, H. Takafuji, T. Kanamoto	An Approach for Reducing Leakage Current Variation Due to Manufacturing Variability	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E92-A(12)	3016--3023	2009年12月	129.pdf
論文誌	A. Kurokawa, T. Sato, T. Kanamoto, M. Hashimoto	Interconnect Modeling: a Physical Design Perspective (Invited)	IEEE Transactions on Electron Devices	56(9)	1840--1851	2009年9月	126.pdf
論文誌	Y. Ogasahara, M. Hashimoto, T. Onoye	All Digital Ring-Oscillator Based Macro for Sensing Dynamic Supply Noise Waveform	IEEE Journal of Solid-State Circuits	44(6)	1745--1755	2009年6月	124.pdf
論文誌	T. Enami, S. Ninomiya, M. Hashimoto	Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems	28(4)	541 - 553	2009年4月	118.pdf
論文誌	T. Okumura, A. Kurokawa, H. Masuda, T. Kanamoto, M. Hashimoto, H. Takafuji, H. Nakashima, N. Ono, T. Sakata, T. Sato	Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	92-A(4)	990--997	2009年4月	119.pdf
論文誌	K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye	An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability	IEICE Trans. on Electronics	E92-C(2)	281--285	2009年2月	117.pdf
論文誌	T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, M. Hashimoto	Impact of Well Edge Proximity Effect on Timing	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E91-A(12)	3461-3464	2008年12月	111.pdf
論文誌	S. Abe, M. Hashimoto, T. Onoye	Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E91-A(12)	3481-3487	2008年12月	112.pdf
論文誌	Y. Mitsuyama, K. Takahashi, R. Imai, M. Hashimoto, T. Onoye, I. Shirakawa	Area-Efficient Reconfigurable Architecture for Media Processing	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E91-A(12)	3651-3662	2008年12月	114.pdf
論文誌	M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera	Timing Analysis Considering Temporal Supply Voltage Fluctuation	IEICE Trans. on Information and Systems	E91-D(3)	655--660	2008年3月	101.pdf
論文誌	Y. Ogasahara, M. Hashimoto, T. Onoye	Measurement and Analysis of Inductive Coupling Noise in 90nm Global Interconnects	IEEE Journal of Solid-State Circuits	43(3)	718--728	2008年3月	99.pdf
論文誌	M. Hashimoto, T. Ijichi, S. Takahashi, S. Tsukiyama, I. Shirakawa	Transistor Sizing of LCD Driver Circuit for Technology Migration	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E90-A(12)	2712--2717	2007年12月	96.pdf
論文誌	Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, T. Onoye	Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop with On-Chip Delay Measurement	IEEE Transactions on Circuits and Systems II	54(10)	868--872	2007年10月	94.pdf
論文誌	Y. Ogasahara, M. Hashimoto, T. Onoye	Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Tradeoff between Wire Cross-Sectional Area and Inductive Crosstalk Effect	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E90-A(4)	724--731	2007年4月	80.pdf
論文誌	H. Kobayashi, N. Ono, T. Sato, J. Iwai, H. Nakashima, T. Okumura, M. Hashimoto	Proposal of Metrics for SSTA Accuracy Evaluation	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E90-A(4)	808--814	2007年4月	81.pdf
論文誌	T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto	Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E89-A(12)	3560-3568	2006年12月	3.pdf
論文誌	T. Sato, J. Ichimiya, N. Ono, M. Hashimoto	On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E89-A(12)	3491-3499	2006年12月	4.pdf
論文誌	T. Kanamoto, S. Akutsu, T. Nakabayashi, T. Ichinomiya, K. Hachiya, A. Kurokawa, H. Ishikawa, S. Muromoto, H. Kobayashi, M. Hashimoto	Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E89-A(12)	3666-3670	2006年12月	5.pdf
論文誌	M. Hashimoto, T. Yamamoto, H. Onodera	Statistical Analysis of Clock Skew Variation in H-Tree Structure	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E88-A(12)	pp.3375-3381	2005年12月	6.pdf
論文誌	T. Sato, M. Hashimoto, H. Onodera	Successive Pad Assignment for Minimizing Supply Voltage Drop	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E88-A,(12)	3429-3436	2005年12月	8.pdf
論文誌	T. Sato, J. Ichimiya, N. Ono, K. Hachiya, M. Hashimoto	On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E88-A(12)	3382-3389	2005年12月	9.pdf
論文誌	T. Miyazaki, M. Hashimoto, H. Onodera	A Performance Prediction of Clock Generation PLLs: a Ring Oscillator Based PLL and an LC Oscillator Based PLL	IEICE Trans. on Electronics	E88-C(3)	437-444	2005年3月	89.pdf
論文誌	金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 小林宏行, 橋本昌宜	遅延計算におけるインダクタンスを考慮すべき配線の統計的選別手法	情報処理学会論文誌	44(5)	1301-1310	2003年5月	21.pdf
国際会議	Y. Tada, M. Hashimoto, M. Miyamura, X. Bai, T. Sakamoto, H. Ochi	Memory and Energy Savings in the FPGA Implementation of Keyword Spotting with Stream Processing	Proceedings of Asia Pacific Conference on Circuits and Systems (APCCAS)			採録済
国際会議	Q. Cheng, Q. Li, Z. Yang, Z. Kong, G. Niu, Y. Liang, J. Li, J. H. Park, W. Liao, H. Awano, T. Sato, L. Lin, M. Hashimoto	A Radiation-Hardened Neuromorphic Imager with Self-Healing Spiking Pixels and Unified Spiking Neural Network for Space Robotics	Digest of Symposium on VLSI Technology and Circuits			2025年6月	pdf
国際会議	Q. Cheng, Qiufeng Li, W. Dong, M. Zhang, R. Zhang, M. Huang, H. Yu, Y. Shi, H. Awano, T. Sato, L. Lin, M. Hashimoto	A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-On-Chip Towards In-Orbit Computing	Proceedings of IEEE Custom Integrated Circuits Conference (CICC)			2025年4月	pdf
国際会議	T. Tanaka, T. Uezono, K. Suenaga, M. Hashimoto	Hardware Error Detection with In-Situ Monitoring of Control Flow-Related Specifications	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)		966 - 973	2025年1月	pdf
国際会議	K. Takeuchi, K. Sakamoto, Y. Tsuchiya, T. Kato, R. Nakamura, A. Takeyama, T. Makino, T. Ohshima, M. Hashimoto, H. Shindo	Cross-Section Prediction Method for Proton Direct Ionization Induced Single Event Upset	Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)			2024年9月
国際会議	K. Takeuchi, T. Kato, M. Hashimoto	An SEU Cross Section Model Reproducing LET and Voltage Dependence in Bulk Planar and FinFET SRAMs	Proceedings of International Symposium on Reliability Physics (IRPS)			2024年4月	pdf
国際会議	R. Mizuno, M. Niikura, T. Y. Saito, T. Matsuzaki, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, N. Kawamura, S. Kawase, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, I. Umegaki, A. Hillier, T. Kawata, K. Kitafuji, Y. Yamaguchi, D. Tomono, F. Minato	In-Beam Activation Measurement of Muon Nuclear Capture Reaction on Si Isotopes	The workshop on frontier nuclear studies with gamma-ray spectrometer arrays (gamma24)			2024年3月
国際会議	K. Suemitsu, K. Matsuoka, T. Sato, M. Hashimoto	Logic Locking Over TFHE for Securing User Data and Algorithms	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)			2024年1月	pdf
国際会議	T. Matsumoto, R. Shirai, M. Hashimoto	A Proof-Of-Concept Prototyping of Reservoir Computing with Quantum Dots and an Image Sensor for Image Classification	IEEE International Conference on Rebooting Computing (ICRC)			2023年12月
国際会議	R. Mizuno, M. Niikura, T. Y. Saito, T. Matsuzaki, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, N. Kawamura, S. Kawase, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, I. Umegaki, A. Hillier, T. Kawata, K. Kitafuji, Y. Yamaguchi, D. Tomono, F. Minato	Muon Nuclear Capture Reaction on 28,29,30si	2023 Fall meeting of APS DNP and JPS			2023年11月
国際会議	M. Niikura, R. Mizuno, S. Manabe, T. Y. Saito, T. Matsuzaki, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, A. Hillier, N. Kawamura, Y. Kawashima, S. Kawase, T. Kawata, K. Kitafuji, F. Minato, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, M. Tampo, D. Tomono, I. Umegaki, Y. Yamaguchi, Y. Watanabe	Nuclear Physics for Muon-Induced Soft Error	Workshop for Computational Technique for Negative Muon Spectroscopy and Elemental Analysis			2023年8月
国際会議	R. Mizuno, M. Niikura, T. Y. Saito, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, N. Kawamura, S. Kawase, T. Matsuzaki, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, I. Umegaki	Study of Muon Capture Reaction on Si Via In-Beam Muon Activation	Advances in Radioactive Isotope Science (ARIS)			2023年6月
国際会議	K. Takami, Y. Gomi, S. Abe, W. Liao, S. Manabe, T. Matsumoto, M. Hashimoto	Characterizing SEU Cross Sections of 12- and 28-nm SRAMs for 6.0, 8.0, and 14.8 MeV Neutrons	Proceedings of International Reliability Physics Symposium (IRPS)			2023年3月	pdf
国際会議	R. Mizuno, M. Niikura, T. Y. Saito, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, N. Kawamura, S. Kawase, T. Matsuzaki, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, I. Umegaki	Study of Muon Capture Reaction on Si Via In-Beam Muon Activation	Topical Workshops on Modern Aspects of Nuclear Structure			2023年2月
国際会議	R. Mizuno, M. Niikura, T. Y. Saito, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, N. Kawamura, S. Kawase, T. Matsuzaki, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, I. Umegaki	Measurement of Muon-Induced Nuclear Transmutation for Si Isotopes	Trans-scale Quantum Science Institute			2022年11月
国際会議	S. Abe, M. Hashimoto, W. Liao, T. Kato, H. Asai, K. Shimbo, H. Matsuyama, T. Sato, K. Kobayashi, Y. Watanabe	A Terrestrial SER Estimation Methodology with Simulation and Single-Source Irradiation Applicable to Diverse Neutron Sources	Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)			2022年10月
国際会議	K. Ito, H. Itsuji, T. Uezono, T. Toba, M. Itoh, M. Hashimoto	Constructing Application-Level GPU Error Rate Model with Neutron Irradiation Experiment	Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)			2022年10月	pdf
国際会議	T. Tanaka, R. Shirai, M. Hashimoto	DC Magnetic Field-Based Analytical Localization Robust to Known Stationary Magnetic Object	Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS)			2022年8月	pdf
国際会議	D. Fujimoto, Y. Kim, Y. Hayashi, N. Homma, M. Hashimoto, T. Sato, J.-L. Danger	SASIMI: Evaluation Board for EM Information Leakage from Large Scale Cryptographic Circuits	IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity			2022年8月	pdf
国際会議	Y. Zhang, H. Itsuji, T. Uezono, T. Toba, M. Hashimoto	Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections	Proceedings of Design, Automation and Test in Europe Conference (DATE)		60-63	2022年3月	pdf
国際会議	T. Hsu, D. Yang, W. Liao, M. Itoh, M. Hashimoto, , J. Liou	Processor SER Estimation with ACE Bit Analysis	Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)			2021年9月
国際会議	T. Cheng, M. Hashimoto	Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling	Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)			2021年5月	pdf
国際会議	T. Tanaka, M. Hashimoto, Y. Takeuchi	Linear Programming Based Reliable Software Performance Model Construction with Noisy CPU Performance Counter Values	Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)			2021年3月
国際会議	Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, M. Hashimoto	Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design	Proceedings of Design, Automation and Test in Europe Conference (DATE)			2021年2月	pdf
国際会議	T. Imagawa, J. Yu, M. Hashimoto, H. Ochi	MUX Granularity-Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA	Proceedings of Design, Automation and Test in Europe Conference (DATE)			2021年2月	pdf
国際会議	T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, M. Hashimoto	Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)		284 -- 290	2021年1月	pdf
国際会議	T. Kato, M. Tampo, S. Takeshita, Y. Miyake, H Tanaka, M. Hashimoto	Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization with Neutrons and Alpha-Particles	IEEE Nuclear and Space Radiation Effects Conference (NSREC)			2020年11月
国際会議	H. Itsuji, T. Uezono, T. Toba, K. Ito, M. Hashimoto	Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing	Proceedings of International Test Conference (ITC)			2020年11月	pdf
国際会議	Y. Zhang, K. Ito, H. Itsuji, T. Uezono, T. Toba, M. Hashimoto	Fault Mode Analysis of Neural Network-Based Object Detection on GPUs with Neutron Irradiation Test	Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)			2020年10月
国際会議	K. Ito, Y. Zhang, H. Itsuji, T. Uezono, T. Toba, M. Hashimoto	Analyzing DUE Errors with Neutron Irradiation Test and Fault Injection to Control Flow	Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)			2020年10月
国際会議	Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, M. Hashimoto	Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling	International Workshop on Logic and Synthesis (IWLS)			2020年7月
国際会議	X. Bai, N. Banno, M. Miyamura, R. Nebashi, K. Okamoto, H. Numata, N. Iguchi, M. Hashimoto, T. Sugibayashi, T. Sakamoto, M. Tada	1.5x Energy-Efficient and 1.4x Operation-Speed Via-Switch FPGA with Rapid and Low-Cost ASIC Migration by Via-Switch Copy	Technical Digest of VLSI Symposium on Technology			2020年6月	pdf
国際会議	R. Doi, X. Bai, T. Sakamoto, M. Hashimoto	Fault Diagnosis of Via-Switch Crossbar in Non-Volatile FPGA	Proceedings of Design, Automation and Test in Europe Conference (DATE)			2020年4月	pdf
国際会議	S. Abe, T. Sato, J. Kuroda, S. Manabe, Y. Watanabe, W. Liao, K. Ito, M. Hashimoto, M. Harada, K. Oikawa, Y. Miyake	Impact of Hydrided and Non-Hydrided Materials Near Transistors on Neutron-Induced Single Event Upsets	Proceedings of International Symposium on Reliability Physics (IRPS)			2020年4月	pdf
国際会議	M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, Y. Araki, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, T. Sugibayashi	Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for AI Applications	Technical Digest of International Solid-State Circuits Conference (ISSCC)		502--503	2020年2月	pdf
国際会議	T. Tanio, J. Yu, M. Hashimoto	Training Data Reduction Using Support Vectors for Neural Networks	Proceedings of Asia-Pacific Signal and Information Processing Association (APSIPA) Annual Summit and Conference (ASC)			2019年11月	pdf
国際会議	T. Mahara, S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, T. Y. Saito, M. Niikura, K. Ninomiya, D. Tomono, A. Sato	Irradiation Test of 65-nm Bulk SRAMs with DC Muon Beam at RCNP-MuSIC Facility	Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)			2019年9月
国際会議	T.-Y. Cheng, J. Yu, M. Hashimoto	Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier	Proceedings of International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)			2019年7月	pdf
国際会議	H. Numata, N. Banno, K. Okamoto, N. Iguchi, H. Hada, M. Hashimoto, T. Sugibayashi, T. Sakamoto, M. Tada	Characterization of Chalcogenide Selectors for Crossbar Switch Used in Nonvolatile FPGA	Proceedings of Silicon Nanoelectronics Workshop			2019年6月	pdf
国際会議	S. Abe, W. Liao, S. Manabe, T. Sato, M. Hashimoto, Y. Watanabe	Impact of Irradiation Side on Neutron-Induced Single Event Upsets in 65-nm Bulk SRAMs	Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)			2018年9月
国際会議	R. Shirai, T. Hirose, M. Hashimoto	A Multifunctional Sensor Node Sharing Coils in Wireless Power Supply, Wireless Communication and Distance Sensing Modes	Proceedings of International NEWCAS Conference		152--156	2018年6月	pdf
国際会議	J. Chen, T. Kanamoto, H. Kando, M. Hashimoto	An On-Chip Load Model for Off-Chip PDN Analysis Considering Interdependency between Supply Voltage, Current Profile and Clock Latency	Proceedings of IEEE Workshop on Signal and Power Integrity (SPI)			2018年5月	pdf
国際会議	T. Nakayama, M. Hashimoto	Hold Violation Analysis for Functional Test of Ultra-Low Temperature Circuits at Room Temperature	Proceedings of International Symposium on VLSI Design, Automation and Test (VLSI-DAT)			2018年4月	pdf
国際会議	R. Shirai, T. Hirose, M. Hashimoto	Dedicated Antenna Less Power Efficient OOK Transmitter for mm-Cubic IoT Nodes	Proceedings of European Microwave Conference (EuMC)		101--104	2017年10月	pdf
国際会議	W. Liao, M. Hashimoto, S. Manabe, Y. Watanabe, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, Y. Miyake	Measurement and Mechanism Investigation of Negative and Positive Muon Induced Upsets in 65nm Bulk SRAMs	Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)			2017年10月
国際会議	S. Manabe, Y. Watanabe, W. Liao, M. Hashimoto, K. Nakano, H. Sato, T. Kin, K. Hamada, M. Tampo, Y. Miyake	Momentum and Supply Voltage Dependencies of SEUs Induced by Low-Energy Negative and Positive Muons in 65-nm UTBB-SOI SRAMs	Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)			2017年10月
国際会議	M. Hashimoto, R. Shirai, Y. Itoh, T. Hirose	Toward Real-Time 3D Modeling System with Cubic-Millimeters Wireless Sensor Nodes (Invited)	Proceedings of IEEE International Conference on ASIC		1087--1091	2017年10月	pdf
国際会議	R. Shirai, J. Kono, T. Hirose, M. Hashimoto	Near-Field Dual-Use Antenna for Magnetic-Field Based Communication and Electrical-Field Based Distance Sensing in mm^3-Class Sensor Node	Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)		124--127	2017年5月	pdf
国際会議	S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, M. Hashimoto	Impedance Matching in Magnetic-Coupling-Resonance Wireless Power Transfer for Small Implantable Devices	Proceedings of IEEE Wireless Power Transfer Conference (WPTC)			2017年5月	pdf
国際会議	K. Hirosue, S. Ukawa, Y. Itoh, T. Onoye, M. Hashimoto	GPGPU-based Highly Parallelized 3D Node Localization for Real-Time 3D Model Reproduction	Proceedings of International Conference on Intelligent User Interfaces (IUI)		173--178	2017年3月	pdf
国際会議	N. Banno, M. Tada, K. Okamoto, N. Iguchi, T. Sakamoto, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi	50x20 Crossbar Switch Block (CSB) with Two-Varistors (a-Si/SiN/a-Si) Selected Complementary Atom Switch for a Highly-Dense Reconfigurable Logic	Technical Digest of IEEE International Electron Devices Meeting (IEDM)			2016年12月	231.PDF
国際会議	Y. Masuda, M. Hashimoto, T. Onoye	Critical Path Isolation for Time-To-Failure Extension and Lower Voltage Operation	Proceedings of International Conference on Computer-Aided Design (ICCAD)			2016年11月	230.pdf
国際会議	Y. Akihara, T. Hirose, S. Masuda, N. Kuroki, M. Numa, M. Hashimoto	Analytical Study of Rectifier Circuit for Wireless Power Transfer Systems	Proceedings of International Symposium on Antennas and Propagation (ISAP)			2016年10月	232.pdf
国際会議	S. Masuda, T. Hirose, Y. Akihara, N. Kuroki, M. Numa, M. Hashimoto	Highly-Efficient Power Transmitter Coil Design for Small Wireless Sensor Nodes	Proceedings of International Symposium on Antennas and Propagation (ISAP)			2016年10月	pdf
国際会議	H. Hihara, A. Iwasaki, N. Tamagawa, M. Kuribayashi, M. Hashimoto, Y. Mitsuyama, H. Ochi, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi	Novel Processor Architecture for Onboard Infrared Sensors (Invited)	Proceedings of SPIE Infrared Remote Sensing and Instrumentation XXIV	9973		2016年8月
国際会議	J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, M. Hashimoto	A Highly-Dense Mixed Grained Reconfigurable Architecture with Overlay Crossbar Interconnect Using Via-Switch	Proceedings of International Conference on Field Programmable Logic and Applications (FPL)			2016年8月	pdf
国際会議	Y. Masuda, M. Hashimoto, T. Onoye	Hardware-Simulation Correlation of Timing Error Detection Performance of Software-Based Error Detection Mechanisms	Proceedings of International On-Line Testing Symposium (IOLTS)		84--89	2016年7月	228.pdf
国際会議	Y. Masuda, M. Hashimoto, T. Onoye	Measurement of Timing Error Detection Performance of Software-Based Error Detection Mechanisms and Its Correlation with Simulation	ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)			2016年3月
国際会議	R. Doi, J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, M. Hashimoto	Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch	ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)			2016年3月
国際会議	N. Banno, M.Tada, K. Okamoto, N. Iguchi, T. Sakamoto, M. Miyamura, Y. Tsuji, H. Hada, H. Ochi, H. Onodera, M. Hashimoto, T. Sugibayashi	A Novel Two-Varistors (a-Si/SiN/a-Si) Selected Complementary Atom Switch (2V-1CAS) for Nonvolatile Crossbar Switch with Multiple Fan-Outs	Technical Digest of IEEE International Electron Devices Meeting (IEDM)		32--35	2015年12月	225.PDF
国際会議	Y. Masuda, M. Hashimoto, T. Onoye	Performance Evaluation of Software-Based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise	Proceedings of International Conference on Computer-Aided Design (ICCAD)		315-322	2015年11月	224.pdf
国際会議	R. Doi, M. Hashimoto, T. Onoye	An Analytic Evaluation on Soft Error Immunity Enhancement Due to Temporal Triplication	Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing (PRDC)			2015年11月
国際会議	S. Iizuka, Y. Masuda, M. Hashimoto, T. Onoye	Stochastic Timing Error Rate Estimation under Process and Temporal Variations	Proceedings of International Test Conference (ITC)			2015年10月	223.pdf
国際会議	Y. Akihara, T. Hirose, Y. Tanaka, N. Kuroki, M. Numa, M. Hashimoto	A Wireless Power Transfer System for Small-Sized Sensor Applications	Proceedings of International Conference on Solid State Devices and Materials (SSDM)		154--155	2015年9月
国際会議	M. Ueno, M. Hashimoto, T. Onoye	Real-Time On-Chip Supply Voltage Sensor and Its Application to Trace-Based Timing Error Localization	Proceedings of International On-Line Testing Symposium (IOLTS)		188--193	2015年7月	222.pdf
国際会議	T. Uemura, T. Kato, S. Okano, H. Matsuyama, M. Hashimoto	Impact of Package on Neutron Induced Single Event Upset in 20 nm SRAM	Proceedings of International Symposium on Reliability Physics (IRPS)			2015年4月	215.pdf
国際会議	T. Uemura, M. Hashimoto	Investigation of Single Event Upset and Total Ionizing Dose in FeRAM for Medical Electronic Tag	Proceedings of International Symposium on Reliability Physics (IRPS)			2015年4月	216.pdf
国際会議	T. Uemura, S. Okano, T. Kato, H. Matsuyama, M. Hashimoto	Soft Error Immune Latch Design for 20 nm Bulk CMOS	Proceedings of International Reliability Physics Symposium (IRPS)			2015年4月	217.pdf
国際会議	S. Ukawa, T. Shinada, M. Hashimoto, Y. Itoh, T. Onoye	3D Node Localization from Node-To-Node Distance Information Using Cross-Entropy Method	Proceedings of Virtual Reality Conference (VR)			2015年3月	218.pdf
国際会議	S. Iizuka, Y. Higuchi, M. Hashimoto, T. Onoye	Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)		731--736	2015年1月	214.pdf
国際会議	M. Hashimoto, D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, K. Wakabayashi, T. Onoye, H. Onodera	Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)		14--15	2015年1月	213.pdf
国際会議	T. Amaki, M. Hashimoto, T. Onoye	An Oscillator-Based True Random Number Generator with Process and Temperature Tolerance	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)		4--5	2015年1月	212.pdf
国際会議	A. Iokibe, M. Hashimoto, T. Onoye	Feasibility Evaluation on an Instant Invader Detection System with Ultrasonic Sensors Scattered on the Ground	Proceedings of International Conference on Sensing Technology (ICST)		188--193	2014年9月	204.pdf
国際会議	T. Uemura, T. Kato, R. Tanabe, H. Iwata, J. Ariyoshi, H. Matsuyama, M. Hashimoto	Optimizing Well-Configuration for Minimizing Single Event Latchup	IEEE Nuclear and Space Radiation Effects Conference (NSREC)			2014年7月
国際会議	T. Uemura, T. Kato, R. Tanabe, H. Iwata, H. Matsuyama, M. Hashimoto, K. Takahisa, M. Fukuda, K. Hatanaka	Preventing Single Event Latchup with Deep P-Well on P-Substrate	Proceedings of International Reliability Physics Symposium (IRPS)			2014年6月	203.pdf
国際会議	M. Ueno, M. Hashimoto, T. Onoye	Trace-Based Fault Localization with Supply Voltage Sensor	ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)		77--81	2014年3月
国際会議	H. Konoura, D. Alnajjar, Y. Mitsuyama, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye	Mixed-Grained Reconfigurable Architecture Supporting Flexible Reliability and C-Based Design	Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig)			2013年12月	199.pdf
国際会議	S. Iizuka, M. Mizuno, D. Kuroda, M. Hashimoto, T. Onoye	Stochastic Error Rate Estimation for Adaptive Speed Control with Field Delay Testing	Proceedings of International Conference on Computer-Aided Design (ICCAD)		107--114	2013年11月	193.PDF
国際会議	J. Kono, M. Hashimoto, T. Onoye	Feasibility Evaluation of Near-Field Communication in Clay with 1-mm^3 Antenna	Proceedings of Asia-Paciﬁc Microwave Conference (APMC)		1121--1123	2013年11月	194.pdf
国際会議	T. Amaki, M. Hashimoto, T. Onoye	A Process and Temperature Tolerant Oscillator-Based True Random Number Generator with Dynamic 0/1 Bias Correction	Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)		133--136	2013年11月	195.pdf
国際会議	D. Alnajjar, H. Konoura, Y. Mitsuyama, H. Shimada, K. Kobayashi, H. Kanbara, H. Ochi, T. Imagawa, S. Noda, K. Wakabayashi, M. Hashimoto, T. Onoye, H. Onodera	Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-To-Array Mapping and Its Radiation Testing	Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)		313--316	2013年11月	196.pdf
国際会議	R. Harada, M. Hashimoto, T. Onoye	NBTI Characterization Using Pulse-Width Modulation	IEEE/ACM Workshop on Variability Modeling and Characterization			2013年11月
国際会議	T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto	Scaling Trend of SRAM and FF of Soft-Error Rate and Their Contribution to Processor Reliability on Bulk CMOS Technology	IEEE Nuclear and Space Radiation Effects Conference (NSREC)			2013年7月
国際会議	T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto	Soft-Error in SRAM at Ultra Low Voltage and Impact of Secondary Proton in Terrestrial Environment	IEEE Nuclear and Space Radiation Effects Conference (NSREC)			2013年7月
国際会議	T. Uemura, T. Kato, H. Matsuyama, M. Hashimoto	Mitigating Multi-Cell-Upset with Well-Slits in 28nm Multi-Bit-Latch	IEEE Nuclear and Space Radiation Effects Conference (NSREC)			2013年7月
国際会議	T. Shinada, M. Hashimoto, T. Onoye	Proximity Distance Estimation Based on Capacitive Coupling between 1mm^3 Sensor Nodes	Proceedings of International NEWCAS Conference			2013年6月	188.pdf
国際会議	M. Ueno, M. Hashimoto, T. Onoye	Real-Time Supply Voltage Sensor for Detecting/Debugging Electrical Timing Failures	Proceedings of Reconfigurable Architectures Workshop (RAW)		301--305	2013年5月	187.pdf
国際会議	D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye	Static Voltage Over-Scaling and Dynamic Voltage Variation Tolerance with Replica Circuits and Time Redundancy in Reconfigurable Devices	Proceedings of International Conference on ReConFigurable Computing and FPGAs (ReConFig)			2012年12月	174.pdf
国際会議	I. Homjakovs, M. Hashimoto, T. Hirose, T. Onoye	Signal-Dependent Analog-To-Digital Converter Based on MINIMAX Sampling	Proceedings of International SoC Design Conference (ISOCC)		120 -- 123	2012年11月	176.pdf
国際会議	R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye	Impact of NBTI-Induced Pulse-Width Modulation on SET Pulse-Width Measurement	Proceedings of European Conference on Radiation and Its Effects on Components and Systems (RADECS)			2012年9月
国際会議	T. Kameda, H. Konoura, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye	A Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture	Proceedings of International Conference on Field Programmable Logic and Applications (FPL)			2012年8月	170.pdf
国際会議	R. Harada, S. Abe, H. Fuketa, T. Uemura, M. Hashimoto, Y. Watanabe	Angular Dependency of Neutron Induced Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM	IEEE Nuclear and Space Radiation Effects Conference (NSREC)			2012年7月
国際会議	R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye	SET Pulse-Width Measurement Eliminating Pulse-Width Modulation and Within-Die Process Variation Effects	Proceedings of International Reliability Physics Symposium (IRPS)			2012年4月	168.PDF
国際会議	S. Kimura, M. Hashimoto, T. Onoye	Body Bias Clustering for Low Test-Cost Post-Silicon Tuning	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)		283--289	2012年2月	167.pdf
国際会議	H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye	Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architecture	Proceedings of International Conference on Field Programmable Logic and Applications (FPL)		189--194	2011年9月	162.pdf
国際会議	Y. Takai, M. Hashimoto, T. Onoye	Power Gating Implementation for Noise Mitigation with Body-Tied Triple-Well Structure	Proceedings of IEEE Custom Integrated Circuits Conference (CICC)			2011年9月	163.pdf
国際会議	T. Kameda, H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye	NBTI Mitigation by Giving Random Scan-In Vectors During Standby Mode	Proceedings of International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS)		152--161	2011年9月
国際会議	I. Homjakovs, M. Hashimoto, T. Hirose, T. Onoye	Signal-Dependent Analog-To-Digital Conversion Based on MINIMAX Sampling	Proceedings of International Midwest Symposium on Circuits and Systems (MWSCAS)			2011年8月	161.pdf
国際会議	T. Amaki, M. Hashimoto, T. Onoye	An Oscillator-Based True Random Number Generator with Jitter Amplifier	Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)		725--728	2011年5月	157.pdf
国際会議	R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye	Neutron Induced Single Event Multiple Transients with Voltage Scaling and Body Biasing	Proceedings of International Reliability Physics Symposium (IRPS)		253--257	2011年4月	156.PDF
国際会議	S. Kimura, M. Hashimoto, T. Onoye	Body Bias Clustering for Low Test-Cost Post-Silicon Tuning	ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)		46--51	2011年4月
国際会議	K. Shinkai, M. Hashimoto, T. Onoye	Extracting Device-Parameter Variations with RO-Based Sensors	ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)		13--18	2011年3月
国際会議	D. Alnajjar, H. Kounoura, Y. Mitsuyama, M. Hashimoto, T. Onoye	MTTF Measurement under Alpha Particle Radiation in a Coarse-Grained Reconfigurable Architecture with Flexible Reliability	IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)			2011年3月
国際会議	T. Amaki, M. Hashimoto, T. Onoye	Jitter Amplifier for Oscillator-Based True Random Number Generator	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)		81--82	2011年1月	153.pdf
国際会議	Y. Takai, M. Hashimoto, T. Onoye	Evaluation of Power Gating Structures Focusing on Power Supply Noise with Measurement and Simulation	Proceedings of IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)		213--216	2010年10月	146.pdf
国際会議	T. Okumura, M. Hashimoto	Setup Time, Hold Time and Clock-To-Q Delay Computation under Dynamic Supply Noise	Proceedings of IEEE Custom Integrated Circuits Conference (CICC)			2010年9月	147.pdf
国際会議	T. Amaki, M. Hashimoto, Y. Mitsuyama, T. Onoye	A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling	Proceedings of International Workshop on Information Security Applications (WISA)		107-121	2010年8月
国際会議	H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye	Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM	Proceedings of International Reliability Physics Symposium (IRPS)		213--217	2010年5月	140.PDF
国際会議	S. Abe, K. Shinkai, M. Hashimoto, T. Onoye	Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors	ACM Great Lake Symposium on VLSI (GLSVLSI)		197--202	2010年5月	143.pdf
国際会議	Y. Takai, Y. Ogasahara, M. Hashimoto, T. Onoye	Measurement of On-Chip I/O Power Supply Noise and Correlation Verification between Noise Magnitude and Delay Increase Due to SSO	Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI)		19--20	2010年5月	139.pdf
国際会議	D. Kuroda, H. Fuketa, M. Hashimoto, T. Onoye	A 16-Bit RISC Processor with 4.18pJ/cycle at 0.5V Operation	Proceedings of IEEE COOL Chips		190	2010年4月	145.pdf
国際会議	H. Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye	Comparative Study on Delay Degrading Estimation Due to NBTI with Circuit/Instance/Transistor-Level Stress Probability Consideration	Proceedings of International Symposium on Quality Electronic Design (ISQED)		646--651	2010年3月	137.pdf
国際会議	R. Harada, Y. Mitsuyama, M. Hashimoto, T. Onoye	Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-inverter-delay Resolution	Proceedings of International Symposium on Quality Electronic Design (ISQED)		839--844	2010年3月	138.pdf
国際会議	T. Enami, K. Shinkai, S. Ninomiya, S. Abe, M. Hashimoto	Statistical Timing Analysis Considering Clock Jitter and Skew Due to Power Supply Noise and Process Variation	ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)		41--46	2010年3月
国際会議	S. Abe, K. Shinkai, M. Hashimoto, T. Onoye	Clock Skew Reduction by Self-Compensating Manufacturing Variability with On-Chip Sensors	ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)		89--94	2010年3月
国際会議	T. Okumura, F. Minami, K. Shimazaki, K. Kuwada, M. Hashimoto	Gate Delay Estimation in STA under Dynamic Power Supply Noise	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)		775 -- 780	2010年1月	132.pdf
国際会議	H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye	Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)		361 -- 362	2010年1月	131.pdf
国際会議	D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, T. Onoye	Soft Error Resilient VLSI Architecture for Signal Processing	Proceedings of IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)		183--186	2009年12月	142.pdf
国際会議	H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye	Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits	Proceedings of IEEE Custom Integrated Circuits Conference (CICC)		215--218	2009年9月	127.pdf
国際会議	K. Hamamoto, M. Hashimoto, Y. Mitsuyama, T. Onoye	Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits	Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)		51--56	2009年8月	125.pdf
国際会議	D. Alnajjar, Y. Ko, T. Imagawa, H. Konoura, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, T. Onoye	Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability	Proceedings of International Conference on Field Programmable Logic and Applications (FPL)		186--192	2009年8月	133.pdf
国際会議	S. Watanabe, M. Hashimoto, T. Sato	A Case for Exploiting Complex Arithmetic Circuits Towards Performance Yield Enhancement	Proceedings of International Symposium on Quality Electronic Design (ISQED)		401--407	2009年3月	122.pdf
国際会議	Y. Ko, D. Alnajjar, Y. Mitsuyama, M. Hashimoto, T. Onoye	Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability	Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)		236--241	2009年3月
国際会議	D. Alnajjar, Y. Ko, T. Imagawa, M. Hiromoto, Y. Mitsuyama, M. Hashimoto, H. Ochi, T. Onoye	A Coarse-Grained Dynamically Reconfigurable Architecture Enabling Flexible Reliability	Proceedings of IEEE Workshop on System Effects of Logic Soft Errors (SELSE)			2009年3月
国際会議	H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye	Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)		266-271	2009年1月	116.pdf
国際会議	T. Enami, M. Hashimoto, T. Sato	Decoupling Capacitance Allocation for Timing with Statistical Noise Model and Timing Analysis	Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD)		420--425	2008年11月	110.pdf
国際会議	Y. Ogasahara, M. Hashimoto, T. Kanamoto, T. Onoye	Measurement of Supply Noise Suppression by Substrate and Deep N-Well in 90nm Process	Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)		397--400	2008年11月	109.pdf
国際会議	H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye	Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-Biased Circuits and Subthreshold Circuits	Proceedings of Workshop on Test Structure Design for Variability Characterization			2008年11月
国際会議	H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye	Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits	Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)		3--8	2008年8月	106.pdf
国際会議	S. Watanabe, M. Hashimoto, T. Sato	Cascading Dependent Operations for Mitigating Timing Variability	Proceedings. of Workshop on Quality-Aware Design (W-QUAD)			2008年6月	105.pdf
国際会議	K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye	Experimental Study on Body-Biasing Layout Style -- Negligible Area Overhead Enables Sufficient Speed Controllability --	Proceedings of ACM Great Lake Symposium on VLSI (GLSVLSI)		387--390	2008年5月	104.pdf
国際会議	T. Enami, S. Ninomiya, M. Hashimoto	Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise	Proceedings of ACM International Symposium on Physical Design (ISPD)		160-167	2008年4月	107.pdf
国際会議	S. Abe, M. Hashimoto, T. Onoye	Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution	Proceedings of International Symposium on Quality Electronic Design (ISQED)		520--525	2008年3月	102.PDF
国際会議	Y. Ogasahara, M. Hashimoto, T. Onoye	Dynamic Supply Noise Measurement Circuit Composed of Standard Cells Suitable for In-Site SoC Power Integrity Verification	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)		107--108	2008年1月	97.pdf
国際会議	K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye	A Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed	Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)		233-237	2007年10月
国際会議	T. Kanamoto, Y. Ogasahara, K. Natsume, K. Yamaguchi, H. Amishiro, T. Watanabe, M. Hashimoto	Impact of Well Edge Proximity Effect on Timing	Proceedings of 37th European Solid-State Device Research Conference (ESSDERC)		115--118	2007年9月	92.pdf
国際会議	Y. Ogasahara, M. Hashimoto, T. Onoye	Dynamic Supply Noise Measurement with All Digital Gated Oscillator for Evaluating Decoupling Capacitance Effect	Proceedings of IEEE Custom Integrated Circuits Conference (CICC)		783--786	2007年9月	90.pdf
国際会議	K. Shinkai, M. Hashimoto, T. Onoye	Future Prediction of Self-Heating in Short Intra-Block Wires	Proceedings of International Symposium on Quality Electronic Design (ISQED)		660-665	2007年3月	82.PDF
国際会議	K. Shinkai, M. Hashimoto, A. Kurokawa, T. Onoye	A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process and Environmental Variability	Proceedings of ACM/IEEE International Conference on Computer-Aided Design (ICCAD)		47-53	2006年11月	22.pdf
国際会議	Y. Ogasahara, M. Hashimoto, T. Onoye	Quantitative Prediction of On-Chip Capacitive and Inductive Crosstalk Noise and Discussion on Wire Cross-Sectional Area Toward Inductive Crosstalk Free Interconnects	Proceedings of IEEE International Conference on Computer Design (ICCD)		70-75	2006年10月	23.pdf
国際会議	Y. Ogasahara, M. Hashimoto, T. Onoye	Measurement of Inductive Coupling Effect on Timing in 90nm Global Interconnects	Proceedings of IEEE Custom Integrated Circuits Conference (CICC)		721-724	2006年9月	24.pdf
国際会議	Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, T. Onoye	Measurement Results of Delay Degradation Due to Power Supply Noise Well Correlated with Full-Chip Simulation	Proceedings of IEEE Custom Integrated Circuits Conference (CICC),		861-864	2006年9月	25.pdf
国際会議	T. Ijichi, M. Hashimoto, S. Takahashi, S. Tsukiyama, I. Shirakawa	Transistor Sizing of LCD Driver Circuit for Technology Migration	Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)	1	I25-I28	2006年7月	28.pdf
国際会議	T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto	Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design	Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI)		227-230	2006年5月	65.pdf
国際会議	K. Shinkai, M. Hashimoto, A. Kurokawa, T. Onoye	A Gate Delay Model Focusing on Current Fluctuation Over Wide-Range of Process Variations	ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)		59-64	2006年2月
国際会議	T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, M. Hashimoto	Effective Si-Substrate Modeling for Frequency-Dependent Interconnect Resistance and Inductance Extraction	Proceedings of International Workshop on Compact Modeling (IWCM)		51-56	2006年1月
国際会議	T. Kouno, M. Hashimoto, H. Onodera	Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis	Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC)		453-456	2005年11月	52.pdf
国際会議	S. Uemura, T. Miyazaki, M. Hashimoto, H. Onodera	Estimation of Maximum Oscillation Frequency for CMOS LCVCOs	Proceedings of IEEJ International Analog VLSI Workshop			2005年10月
国際会議	Y. Ogasahara, M. Hashimoto, T. Onoye	Measurement and Analysis of Delay Variation Due to Inductive Coupling	Proceedings of IEEE Custom Integrated Circuits Conference (CICC)		305-308	2005年9月	26.pdf
国際会議	M. Hashimoto, T. Yamamoto, H. Onodera	Statistical Analysis of Clock Skew Variation in H-Tree Structure	Proceedings of International Symposium on Quality Electronic Design (ISQED)		402-407	2005年3月	51.PDF
国際会議	T. Sato, M. Hashimoto, H. Onodera	Successive Pad Assignment Algorithm to Optimize Number and Location of Power Supply Pad Using Incremental Matrix Inversion	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)		723-728	2005年1月	31.pdf
国際会議	M. Hashimoto, J. Yamaguchi, T. Sato, H. Onodera	Timing Analysis Considering Temporal Supply Voltage Fluctuation	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)		1098-1101	2005年1月	32.pdf
国際会議	T. Sato, N. Ono, J. Ichimiya, K. Hachiya, M. Hashimoto	On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)		1074-1077	2005年1月	34.pdf
国際会議	T. Sato, M. Hashimoto, H. Onodera	An IR-drop Minimization by Optimizing Number and Location of Power Supply Pads	Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)		66-72	2004年10月
国際会議	M. Hashimoto, T. Yamamoto, H. Onodera	Statistical Analysis of Clock Skew Variation	Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)		214-219	2004年10月
国際会議	T. Miyazaki, M. Hashimoto, H. Onodera	A Performance Prediction of Clock Generation PLLs: a Ring Oscillator Based PLL and an LC Oscillator Based PLL	IEEJ International Analog VLSI Workshop		45-50	2004年10月
国際会議	T. Miyazaki, M. Hashimoto, H. Onodera	A Performance Comparison of PLLs for Clock Generation Using Ring Oscillator VCO and LC Oscillator in a Digital CMOS Process	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)		545-546	2004年1月	36.pdf
国際会議	T. Sato, T. Kanamoto, A. Kurokawa, Y. Kawakami, H. Oka, T. Kitaura, H. Kobayashi, M. Hashimoto	Accurate Prediction of the Impact of On-Chip Inductance on Interconnect Delay Using Electrical and Physical Parameters	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)		149-155	2003年1月	40.pdf
国際会議	H. Onodera, M. Hashimoto, T. Hashimoto	ASIC Design Methodology with On-Demand Library Generation	Proceedings of Symposium on VLSI Circuits		57-60	2001年6月	59.pdf
国際会議	T. Iwahashi, T. Shibayama, M. Hashimoto, K. Kobayashi, H. Onodera	Vector Quantization Processor for Mobile Video Communication	Proceedings of IEEE International ASIC/SOC Conference		75-79	2000年9月	61.pdf
国内会議(査読付き)	小笠原泰弘, 橋本昌宜, 尾上孝雄	LSI 配線における容量性, 誘導性クロストークノイズの定量的将来予測	第19回回路とシステム(軽井沢)ワークショップ		5-10	2006年4月	73.pdf
国内会議(査読付き)	新開健一, 橋本昌宜, 黒川敦, 尾上孝雄	電流変動に着目した広範囲な製造・環境ばらつき対応ゲート遅延モデル	第19回回路とシステム(軽井沢)ワークショップ		559-564	2006年4月	75.pdf
国内会議(査読付き)	小林宏行, 小野信任, 佐藤高史, 岩井二郎, 橋本昌宜	統計的STAの有効性の検証手法	第19回回路とシステム(軽井沢)ワークショップ		553-558	2006年4月	74.pdf
国内会議(査読付き)	佐藤高史, 市宮淳次, 小野信任, 蜂屋孝太郎, 橋本昌宜	フロアプランにおけるオンチップ熱ばらつきの解析と対策	情報処理学会DAシンポジウム		133-138	2004年7月
国内会議(査読付き)	金本俊幾, 阿久津滋聖, 中林太美世, 一宮敬弘, 蜂屋孝太郎, 石川博, 室本栄, 小林宏行, 橋本昌宜, 黒川敦	遅延計算およびシグナルインテグリティを考慮した配線寄生容量抽出精度評価	情報処理学会DAシンポジウム		265-270	2004年7月
国内会議(査読付き)	金本俊幾, 佐藤高史, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜	0.1μm級LSIの遅延計算における寄生インダクタンスを考慮すべき配線の統計的選別手法	情報処理学会DAシンポジウム		149-154	2002年7月
国内会議(査読付き)	佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜	インダクタンスが配線遅延に及ぼす影響の定量的評価方法	第15回回路とシステム(軽井沢)ワークショップ		493-498	2002年4月
研究会・全国大会等	R. Mizuno, M. Niikura, T. Y. Saito, T. Matsuzaki, S. Abe, H. Fukuda, M. Hashimoto, K. Ishida, N. Kawamura, S. Kawase, M. Oishi, P. Strasser, A. Sato, K. Shimomura, S. Takeshita, I. Umegaki, A. Hillier, T. Kawata, K. Kitafuji, D. Tomono	ミューオン原子核捕獲反応による生成核分岐比の測定	第12回停止・低速RIビームを用いた核分光研究会 (12th SSRI)			2023年9月
研究会・全国大会等	T.-Y. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, M. Hashimoto	Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization	電子情報通信学会 VLSI設計技術研究会			2021年3月
研究会・全国大会等	J. Hotate, T. Kishimoto, T. Higashi, H. Ochi, R. Doi, M. Tada, T. Sugibayashi, K. Wakabayashi, H. Onodera, Y. Mitsuyama, M. Hashimoto	Highly-Dense Mixed Grained Reconfigurable Architecture with Via-Switch	Work in Progress Session, Design Automation Conference (DAC)			2016年6月
研究会・全国大会等	S. Iizuka, Y. Higuchi, M. Hashimoto, T. Onoye	Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator	電子情報通信学会 VLSI設計技術研究会			2015年3月
研究会・全国大会等	M. Hashimoto, M. Ueno, T. Onoye	Real-Time Supply Voltage Sensor for Trace-Based Fault Localization	Poster Session, International Test Conference (ITC)			2014年10月
研究会・全国大会等	I. Homjakovs, M. Hashimoto, T. Hirose, T. Onoye	Signal-Dependent Analog-To-Digital Conversion Based on Minimax	電子情報通信学会集積回路研究会	( ICD2011-121)	105--107	2011年12月
研究会・全国大会等	小笠原泰弘, 榎並孝司, 橋本昌宜, 佐藤高史、尾上孝雄	電源ノイズによる遅延変動の測定とフルチップシミュレーションによる遅延変動の再現	電子情報通信学会集積回路研究会,	(ICD2006-174)		2007年1月
研究会・全国大会等	小笠原泰弘, 橋本昌宜, 尾上孝雄	90nm グローバル配線における誘導性クロストークノイズによる遅延変動の実測	電子情報通信学会集積回路研究会	(ICD2006-173)		2007年1月
研究会・全国大会等	Jangsombatsiri Siriporn, 橋本昌宜, 尾上孝雄	シャントコンダクタンスを挿入したオンチップ伝送線路特性評価	第十回シリコンアナログRF研究会			2006年11月
研究会・全国大会等	小笠原泰弘, 新開健一, 榎並孝司, 阿部慎也, 二宮進有, 橋本昌宜	ナノメートル世代のVLSIタイミング設計技術の研究	第10回システムLSIワークショップ		195-198	2006年11月
研究会・全国大会等	新開健一, 橋本昌宜, 尾上孝雄	短距離ブロック内配線の自己発熱問題の将来予測	2006年電子情報通信学会ソサイエティ大会講演論文集	(A-3-14)		2006年9月	72.pdf
研究会・全国大会等	伊地知孝仁, 橋本昌宜，高橋真吾，築山修治，白川功	画素充電率制約を満足する液晶ドライバ回路のトランジスタサイズ決定技術	電子情報通信学会 VLSI設計技術研究会	(VLD2005-131)		2006年3月
研究会・全国大会等	榎並孝司, 橋本昌宜, 尾上孝雄	電源ノイズ解析のための回路動作部表現法の評価	2006年電子情報通信学会総合大会講演論文集	(A-3-15)		2006年3月	77.pdf
研究会・全国大会等	小笠原泰弘, 橋本昌宜, 尾上孝雄	誘導性・容量性クロストークノイズによる遅延変動の測定と評価	電子情報通信学会集積回路研究会	(ICD2005-74)		2005年8月
研究会・全国大会等	宮崎崇仁, 橋本昌宜, 小野寺秀俊	デジタルCMOSプロセスを使用したクロック生成向けPLLの将来性能予測ーLC発振型VCOを用いたPLLの有効性ー	電子情報通信学会集積回路研究会	(ICD2003-99)	29-34	2003年9月
研究会・全国大会等	宮崎崇仁, 新名亮規, 橋本昌宜, 小野寺秀俊	オンチップオシロ用サンプルホールド回路の広周波数帯域化	2003年電子情報通信学会総合大会講演論文集	(C-12-34)	103	2003年3月
研究会・全国大会等	佐藤高史, 金本俊幾, 黒川敦, 川上善之, 岡宏規, 北浦智靖, 池内敦彦, 小林宏行, 橋本昌宜	インダクタンスに起因する配線遅延変動の統計的予測手法	2002年電子情報通信学会ソサイエティ大会講演論文集	(TA-2-4)	247-248	2002年9月
研究会・全国大会等	橋本昌宜, 橋本鉄太郎, 西川亮太, 福田大輔, 黒田慎介, 菅俊介, 神原弘之, 小野寺秀俊	オンデマンドライブラリを用いたシステムLSI詳細設計手法	電子情報通信学会VLSI設計技術研究会	(VLD99-112/ICD99-269)		2000年3月
研究会・全国大会等	橋本昌宜, 橋本鉄太郎，西川亮太，福田大輔，黒田慎介，菅俊介，神原弘之，小野寺秀俊	オンデマンドライブラリを用いたシステムLSI詳細設計手法	第3回システムLSI琵琶湖ワークショップ		279-281	1999年11月
著書	H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada, M. Miyamura, T. Sakamoto	Atomic Switch FPGA: Application for IoT Sensing Systems in Space	Book Chapter, Atomic Switch, Springer			2020年3月
著書	E. Ibe, S. Yoshimoto, M. Yoshimoto, H. Kawaguchi, K. Kobayashi, J. Furuta, Y. Mitsuyama, M. Hashimoto, T. Onoye, H. Kanbara, H. Ochi, K. Wakabayashi, H. Onodera, M. Sugihara	Radiation-Induced Soft Errors	Book chapter, VLSI Design and Test for Systems Dependability, Springer			2018年8月
著書	H. Hihara, A. Iwasaki, M. Hashimoto, H. Ochi, Y. Mitsuyama, H. Onodera, H. Kanbara, K. Wakabayashi, T. Sugibayashi, T. Takenaka, H. Hada, M. Tada	Applications of Reconfigurable Processors as Embedded Automatons in the IoT Sensor Networks in Space	Book chapter, VLSI Design and Test for Systems Dependability, Springer			2018年8月
著書	T. Sato, M. Hashimoto, S. Tanakamaru, K. Takeuchi, Y. Sato, S. Kajihara, M. Yoshimoto, J. Jung, Y. Kimi, H. Kawaguchi, H. Shimada, J. Yao	Time-Dependent Degradation in Device Characteristics and Countermeasures by Design	Book chapter, VLSI Design and Test for Systems Dependability, Springer			2018年8月