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	著者名 (author)	表題 (title)	論文誌/会議名	巻号	ページ範囲 (pages)	出版年月	File
論文誌	T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, M. Hashimoto	Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	E105-A(3)	497--508	2022年3月	pdf
論文誌	Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, , M. Hashimoto	Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling	IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences	105-A(3)	509--517	2022年3月	pdf
論文誌	T. Cheng, Y. Masuda, J. Chen, J. Yu, M. Hashimoto	Logarithm-Approximate Floating-Point Multiplier Is Applicable to Power-Efficient Neural Network Training	Integration, the VLSI Journal	74	19--31	2020年9月	pdf
国際会議	Q. Cheng, Q. Li, Z. Yang, Z. Kong, G. Niu, Y. Liang, J. Li, J. H. Park, W. Liao, H. Awano, T. Sato, L. Lin, M. Hashimoto	A Radiation-Hardened Neuromorphic Imager with Self-Healing Spiking Pixels and Unified Spiking Neural Network for Space Robotics	Digest of Symposium on VLSI Technology and Circuits			2025年6月	pdf
国際会議	Q. Cheng, Qiufeng Li, W. Dong, M. Zhang, R. Zhang, M. Huang, H. Yu, Y. Shi, H. Awano, T. Sato, L. Lin, M. Hashimoto	A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-On-Chip Towards In-Orbit Computing	Proceedings of IEEE Custom Integrated Circuits Conference (CICC)			2025年4月	pdf
国際会議	T. Cheng, M. Hashimoto	Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling	Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)			2021年5月	pdf
国際会議	Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, M. Hashimoto	Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design	Proceedings of Design, Automation and Test in Europe Conference (DATE)			2021年2月	pdf
国際会議	T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, M. Hashimoto	Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization	Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC)		284 -- 290	2021年1月	pdf
国際会議	Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, M. Hashimoto	Variation-Tolerant Voltage Over-Scalable Design with Critical Path Isolation and Bit-Width Scaling	International Workshop on Logic and Synthesis (IWLS)			2020年7月
国際会議	T.-Y. Cheng, J. Yu, M. Hashimoto	Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier	Proceedings of International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)			2019年7月	pdf
研究会・全国大会等	T.-Y. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, M. Hashimoto	Mode-Wise Voltage-Scalable Design with Activation-Aware Slack Assignment for Energy Minimization	電子情報通信学会 VLSI設計技術研究会			2021年3月