この検索内の頻出タグ: accelerator^:3 neural^:3 accelerators^:2 computing^:2 dnn^:2 impact^:2 inference^:2 multiplier^:2 network^:2 soc^:2 system-on-chip^{:2 :1} 13-34^:1 22nm^:1 8-bit^:1 88.5^:1 accurately^:1 ai^:1 architecture-independent^:1 be^:1 black-box/white-box^:1 booth^:1 booth-value-confined^:1 can^:1 case^:1 cases?^:1 compensation^:1 contiguity-aware^:1 convolutional^:1 dbc^:1

10 件の該当がありました． : このページのURL : HTML

論文誌

[1] W. Jin, Q. Cheng, Y. Liang, and M. Hashimoto, "An 88.5 fsrms Integrated Jitter and ‒76.2 dBc Reference Spur mmW PLL Utilizing a Ripple Compensation Phase/Frequency Detector," IEEE Transactions on Circuits and Systems I: Regular Papers, 採録済. [pdf]

[2] Q. Cheng, M. Huang, C. Man, A. Shen, L. Dai, H. Yu, and M. Hashimoto, "Reliability Exploration of System-On-Chip with Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks," IEEE Transactions on Circuits and Systems I: Regular Papers, volume 70, number 10, 3978 -- 3991, October 2023. [pdf]

[3] Q. Cheng, L. Dai, M. Huang, A. Shen, W. Mao, M. Hashimoto, and H. Yu, "A Low-Power Sparse Convolutional Neural Network Accelerator with Pre-Encoding Radix-4 Booth Multiplier," IEEE Transactions on Circuits and Systems II, volume 70, number 6, 2246 - 2250, June 2023. [pdf]

国際会議

[1] Q. Cheng, Q. Li, Z. Yang, Z. Kong, G. Niu, Y. Liang, J. Li, J. H. Park, W. Liao, H. Awano, T. Sato, L. Lin, and M. Hashimoto, "A Radiation-Hardened Neuromorphic Imager with Self-Healing Spiking Pixels and Unified Spiking Neural Network for Space Robotics," Digest of Symposium on VLSI Technology and Circuits, 採録済.

[2] Q. Cheng, Qiufeng Li, W. Dong, M. Zhang, R. Zhang, M. Huang, H. Yu, Y. Shi, H. Awano, T. Sato, L. Lin, and M. Hashimoto, "A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-On-Chip Towards In-Orbit Computing," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), April 2025. [pdf]

[3] Q. Cheng, W. Liao, R. Zhang, H. Yu, L. Lin, and M. Hashimoto, "HachiFI: a Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact Evaluation," Proceedings of Design, Automation and Test in Europe Conference (DATE), March 2025. [pdf]

[4] M. Zhang, Q. Cheng, H. Awano, L. Lin, and M. Hashimoto, "S3M: Static Semi-Segmented Multipliers for Energy-Efficient DNN Inference Accelerators," Proceedings of IEEE International Conference on Computer Design (ICCD), pages 16-23, October 2024. [pdf]

[5] Q Cheng, L. Lin, M. Huang, Q. Li, Z. Yang, L. Dai, H. Yu, Y-J. Chen, Y. Shi, and M. Hashimoto, "A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping," Technical Digest of Asian Solid-State Circuits Conference (A-SSCC), October 2024. [pdf]

[6] Q. Cheng, Q. Li, L. Lin, W. Liao, L. Dai, H. Yu, and M. Hashimoto, "How Accurately Can Soft Error Impact Be Estimated in Black-Box/White-Box Cases? -- a Case Study with an Edge AI SoC --," Proceedings of Design Automation Conference (DAC), June 2024. [pdf]

国内会議(査読付き)

[1] Zhang Mingtao, Cheng Quan, 粟野 皓光, Lin Longyang, 橋本 昌宜, "Squeezing 8-Bit Multiplier Energy with Input Segmentation in DNN Inference Accelerators," 情報処理学会DAシンポジウム, 2024年.