論文誌
[1] W. Liao and M. Hashimoto, "Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate," IEICE Trans. on Electronics, volume E102-C, number 4, pages 296--302, April 2019.
国際会議
[1] L. Zhang, B. Li, and M. Hashimoto. U. Schlichtmann, "VirtualSync: Timing Optimization by Synchronizing Logic Waves with Sequential and Combinational Components as Delay Units," Proceedings of Design Automation Conference (DAC), June 2018.
[2] W. Liao, S. Hirokawa, R. Harada, and M. Hashimoto, "Contributions of SRAM, FF and Combinational Circuit to Chip-Level Neutron-Induced Soft Error Rate -- Bulk vs. FD-SOI at 0.5 and 1.0V --," Proceedings of International NEWCAS Conference, pages 33-37, June 2017.