論文誌
[1] M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, and C.-K. Cheng, "Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E91-A, number 12, pages 3474-3480, December 2008.
[2] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling," IEICE Trans. on Electronics, volume E90-C, number 6, pages 1267-1273, June 2007.
[3] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3585-3593, December 2006.
[4] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E89-A, number 12, pages 3560-3568, December 2006.
[5] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E88-A, number 4, pages 885-891, April 2005.
[6] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Representative Frequency for Interconnect R(f)L(f)C Extraction," IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, volume E86-A, number 12, pages 2942-2951, December 2003.
[7] 土谷亮, 橋本昌宜, 小野寺秀俊, "VLSI配線の伝送線路特性を考慮した駆動力決定手法," 情報処理学会論文誌, volume 43, number 5, pages 1338--1347, 2002年5月.
国際会議
[1] L. Zhang, Y. Zhang, A. Tsuchiya, M. Hashimoto, E. Kuh, and C-K Cheng, "High Performance On-Chip Differential Signaling Using Passive Compensation for Global Communication," Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 385--390, January 2009.
[2] Y. Zhang, L. Zhang, A. Tsuchiya, M. Hashimoto, and C.-K. Cheng, "On-Chip High Performance Signaling Using Passive Compensation," Proceedings of IEEE International Conference on Computer Design (ICCD), pages 182-187, October 2008.
[3] M. Hashimoto, J. Siriporn, A. Tsuchiya, H. Zhu, and Chung-Kuan Cheng, "Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration," Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 869--872, September 2007.
[4] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Si-Substrate Modeling Toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design," In Proceedings of IEEE Wrokshop on Signal Propagation on Interconnects (SPI), pages 227-230, May 2006.
[5] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Interconnect RL Extraction at a Single Representative Frequency," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 515-520, January 2006.
[6] T. Kanamoto, T. Ikeda, A. Tsuchiya, H. Onodera, and M. Hashimoto, "Effective Si-Substrate Modeling for Frequency-Dependent Interconnect Resistance and Inductance Extraction," In Proceedings of International Workshop on Compact Modeling (IWCM), pages 51-56, January 2006.
[7] M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, "Performance Prediction of On-Chip High-Throughput Global Signaling," In Proceedings of IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pages 79-82, October 2005.
[8] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Design Guideline for Resistive Termination of On-Chip High-Speed Interconnects," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 613-616, September 2005.
[9] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Substrate Loss of On-Chip Transmission-Lines with Power/Ground Wires in Lower Layer," In Proceedings of IEEE Workshop on Signal Propagation on Interconnects (SPI), pages 201-202, May 2005.
[10] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Effects of Orthogonal Power/Ground Wires on On-Chip Interconnect Characteristics," In Proceedings of International Meeting for Future of Electron Devices, Kansai, pages 33-34, April 2005.
[11] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Return Path Selection for Loop RL Extraction," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 1078-1081, January 2005.
[12] M. Hashimoto, A. Tsuchiya, A. Shinmyo, and H. Onodera, "Performance Prediction of On-Chip Global Signaling," In IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), pages 87-100, November 2004.
[13] M. Hashimoto, A. Tsuchiya, and H. Onodera, "On-Chip Global Signaling by Wave Pipelining," In IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pages 311-314, October 2004.
[14] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling," In Proceedings of IEEE Custom Integrated Circuits Conference (CICC), pages 489-492, September 2004.
[15] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Representative Frequency for Interconnect R(f)L(f)C Extraction," In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC), pages 691-696, January 2004.
[16] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Frequency Determination for Interconnect RLC Extraction," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 288-293, April 2003.
[17] M. Hashimoto, D. Hiramatsu, A. Tsuchiya, and H. Onodera, "Interconnect Structures for High-Speed Long-Distance Signal Transmission," In Proceedings of IEEE International ASIC/SOC Conference, pages 426-430, September 2002.
[18] A. Tsuchiya, M. Hashimoto, and H. Onodera, "Driver Sizing for High-Performance Interconnects Considering Transmission-Line Effects," In Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), pages 377-381, October 2001.
国内会議(査読付き)
[1] 土谷亮, 橋本昌宜, 小野寺秀俊, "配線の伝達特性ﾉ基づく抽出周波数決定手法," 情報処理学会DAシンポジウム, pages 169-174, 2005年8月.
[2] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ高速信号伝送における終端抵抗決定手法," 第18回 回路とシステム(軽井沢)ワークショップ, pages 425-430, 2005年4月.
[3] 土谷亮, 橋本昌宜, 小野寺秀俊, "配線RL抽出におけるリターンパス選択手法," 情報処理学会DAシンポジウム, pages 175-180, 2004年7月.
[4] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ伝送線路のリターン電流分布が信号波形に与える影響 --- 平衡・不平衡伝送の比較 ---," 第17回 回路とシステム(軽井沢)ワークショップ, pages 567-572, 2004年4月.
[5] 土谷亮, 橋本昌宜, 小野寺秀俊, "直交配線を持つオンチップ伝送線路の特性評価," 情報処理学会DAシンポジウム, pages 133-138, 2003年7月.
[6] 土谷亮, 橋本昌宜, 小野寺秀俊, "配線R(f)L(f)C抽出のための代表周波数決定手法," 第16回 回路とシステム(軽井沢)ワークショップ, pages 61-66, 2003年4月.
[7] 平松大輔, 土谷亮, 橋本昌宜, 小野寺秀俊, "長距離高速信号伝送を可能にするVLSI配線構造の検討," 情報処理学会DAシンポジウム, pages 155-160, 2002年7月.
研究会・全国大会等
[1] 上村晋一朗, 土谷亮, 橋本昌宜, 小野寺秀俊, "ロードマップに準拠したSPICEトランジスタモデルの構築," 2006年電子情報通信学会総合大会講演論文集, number A-3-16, 2006年3月.
[2] 土谷亮, 新名亮規, 橋本昌宜、小野寺秀俊, "CMLを用いたオンチップ長距離高速信号伝送技術の開発," 第9回システムLSIワークショップ, pages 275-278, 2005年11月.
[3] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ高速信号伝送用配線の解析的性能評価," 電子情報通信学会 VLSI設計技術研究会, number VLD2004-145, 2005年3月.
[4] 土谷亮, 橋本昌宜, 小野寺秀俊, "実測と電磁界解析による基板損失の評価," 第三回シリコンアナログRF研究会, 2005年1月.
[5] 土谷亮, 橋本昌宜, 小野寺秀俊, "基板および周辺信号配線が配線特性に及ぼす影響の実測," 第二回シリコンアナログRF研究会, 2004年8月.
[6] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ伝送線路におけるリターン電流評価精度が信号波形に与える影響," 第一回シリコンアナログRF研究会, 2004年4月.
[7] 土谷亮, 橋本昌宜, 小野寺秀俊, "オンチップ高速信号配線における波形歪みの影響," 2003年電子情報通信学会ソサイエティ大会講演論文集, number A-3-6, page 56, 2003年9月.
[8] 土谷亮, 橋本昌宜, 小野寺秀俊, "信号配線と下層配線との結合に対する直交配線の影響," 2003年電子情報通信学会総合大会講演論文集, number A-3-14, page 81, 2003年3月.
[9] 土谷亮, 橋本昌宜, 小野寺秀俊, "LSI配線インダクタンスに対する直交配線の影響," 2002年電子情報通信学会総合大会講演論文集, number A-3-23, page 102, 2002年3月.
[10] 土谷亮, 橋本昌宜, 小野寺秀俊, "長距離高速配線における RC モデルに基づく回路設計の限界," 2001年電子情報通信学会ソサイエティ大会講演論文集, number A-3-6, page 60, 2001年9月.